1. Field of the Invention
The present invention relates to photolithography techniques and photolithographic masks and methods for fabricating such masks.
2. Description of Related Art
Dimensions of integrated circuit continue to become smaller in order to fit more circuitry in a given area. Features of integrated circuits that must continue to shrink include patterned conductor layers in which “interconnects” are formed for parts of the integrated circuit. As a result the shrinking node sizes on integrated circuits, the distance between conductors in the layers of patterned conductors has also decreased. A via is a hole through a layer or layers of material in an integrated circuit, which is typically filled with a conductor, sometimes called a plug, that can provide an interlayer connector between or among the layers of patterned conductors. So, as the distance between patterned conductors has decreased, there is increased pressure to make vias in smaller and smaller pitches.
Vias can be created through lithography, in which a group of via features on a mask defines an optical projection onto a wafer used in processes to form the vias on the wafer according to the pattern in the mask. With decreased via sizes, optical proximity correction (hereinafter OPC) features are included with the via features in the mask.
A via pattern on a mask can therefore include both the via feature and any OPC feature that is associated with such via feature. While the use of OPC features reduces distortion, such use also increases the area of each via pattern on the mask. Such increased area of each via pattern conflicts with the decreasing spacing between vias on the circuits being manufactured.
It is therefore desirable to provide technology which supports the use of OPC features despite the decreasing spacing between vias.